LiteX SATA demo¶
This example design features a Litex SoC based around VexRiscv soft CPU. It also includes a DDR controller and a SATA core.
To build the litex SATA demo example, first re-navigate to the directory that contains examples for Xilinx 7-Series FPGAs. Then depending on your hardware, run:
TARGET=”nexys_video” make -C litex_sata_demo
At completion, the bitstreams are located in the build directory:
To generate the source files for this test, the following packages were used:
The generated verilog design file (litesata.v) contains a couple of fixes to properly work with the Yosys+VPR flow. The fixes are around the GTP high speed transceivers hard blocks.